This disclosure is relevant to interfaces which encode and decode data values as transitions on the interconnect medium and have redundant resources to bypass faulty connections. Examples of such codes are described in Shokrollahi I, including the FTTL4 code utilized as a descriptive example herein. Efficient hardware-based identification of faulty connections is desired to facilitate automated reconfiguration of the redundant resources. The disclosed invention is relevant generally to any interface using transition codes, but is of particular interest to interfaces of 3D chip stacks where the interconnect is composed of stacked Thru-Silicon Vias (TSVs).
FIG. 1 provides a model of the general case, where the transmission of data across an interface is characterized by the number of wires (n) and the number of allowed electrical states on each wire (s). The term “wire” is used within this disclosure to refer generally to one element of the interconnect medium, without limitation to e.g. metallic electrical connection for such medium.) For a state based code, data values of m bits width are encoded into corresponding codewords represented by a unique combination of states on the n wires. The state levels of the wires are detected at the receive end of the interface and decoded to reproduce the original data value.
Note that in the general case m and n are not necessarily equal. If the number of possible electrical states s of each wire is greater than 2 (i.e. multi-level signaling is employed), then it is possible to encode m data bits into n wires where n<m.
Another method of encoding data bits onto the wires of the interface is to define codewords based on whether or not a transition occurs on each wire rather than the actual state of the wire. The current state of the wire is irrelevant to a transition code; the receiver detects whether transitions occur on each wire and decodes the codeword accordingly.
If s>2, then it is possible to define more than one type of transition. The receiver can differentiate between types of transitions based on the origin and terminal states of the wire. This expands the available code space such that transition codes where n<m are possible.
Transition codes are one type of code that can be used on interfaces between chips of a three dimensional (3D) chip stack. The 3D chip stack for a typical application is shown in FIG. 2 where a controller chip on the bottom of the stack connects to multiple DRAM chips. In one such embodiment, write data is broadcast by the controller chip to DRAM chips (egress path), and DRAM chips respond on a tri-state bus to the controller chip (ingress path). The interconnections between chips are composed of Thru-Silicon Vias (TSVs) which provide a high density of I/O for a given chip area. However, TSV yield is a significant factor in the manufacturing process for 3D chip stacks, and interconnect redundancy is desirable to mitigate yield impacts.
FIG. 3 illustrates an embodiment of the data transmission path of FIG. 1 with data steering stages added to support an interconnect that has one redundant wire available. Since the codeword requires n wires, and n+1 wires are available, then a fault on any one wire can be bypassed. Other embodiments may include more than one redundant wire, and thus may support correction of additional faults.
It is desirable to transmit a test pattern over the interface in FIG. 3 and check the pattern at the receive end to determine if the n wires being used are free from faults. Such test patterns may be implemented as a Built-In-Self-Test (BIST) feature of the interface, or may be generated external to the chip and applied by manufacturing test equipment to test the interface as part of a manufacturing or assembly process. If a fault is detected, it is desirable for the Pattern Checker to isolate which wire contains the fault based on the received test pattern. The data steering can be reconfigured based on this detection to bypass the wire with the fault. Known techniques exist for detecting and isolating stuck faults on wires using binary state-based codes. However, these techniques do not work with transition codes where the mapping between data bits and wires is not one-for-one.
Furthermore, it is desirable to minimize the required test circuitry incorporated into the DRAM chips shown in the application in FIG. 2. Toward this end, the DRAM is simplified to loopback the egress path to the ingress path with minimal processing as shown for the Data Loopback 420 in the loopback path of FIG. 4. The Pattern Generator 410 and Pattern Checker 430 are both located on the controller chip. This architecture places the additional burden on the test pattern, in that faults on the egress path must be distinguishable from faults on the ingress path.